Low-Power Embedded Processor

Team Report #14 (3/29/04)

Last Week:

1. We finished integrating all the components of our processor.
2. We have been testing all the functionality of our design.  So far, we have identified several problems and corrected them.

 Next Week:

1. We will continue to do more testing.
2. We will start working on synthesis of our VHDL code.

Team Report #13 (3/15/04)

Last Week:

1. Worked on integrating the different parts of the processor.
2. Made a few posters for our presentation.
3. Worked on the low power implementation of the ALU

Next Week:

1. We will start testing our integrated design.
2. We will start to gather ideas for the final report.
3. Integrate all the low power modification to the overall architecture.  

Team Report #12 (3/2/04)

Last Week:

1. We designed the 12-bit adder.
2. Updated Stages.
3. Put together the execute stage
4. And came up with poster layouts for our presentation.

Next Week:

1. Will work on clock gating for the ALU.
2. Continue our work on integrating all the different components.
3. Make the necessary changes on our poster layout.

Team Report #11 (2/23/04)

Last Week:

1. Updated the instruction summery.
2. Worked on the ALU code.
3. Worked on Clock gating.

Next Week:

1. Our team will redesign problems with ALU.
2. Will do some research on memory design.
3. The branch adder will be changed to accommodate 12-bit addition.
4. We will work on the posters for our final presentation.

Team Report #10 (2/17/04)

 Last Week:

1. Worked on the ALU coding and clockgating.
2. Worked on documentation and instruction summary.

Next Week:

1. More research on sleep mode.
2. Updating instruction summary.
3. And we will finish up the ALU without clockgating.
4. We will try to put everything together.

Team Report #9 (1/26/04):

Last Week:

1. Gathered necessary information regarding clock gating.
2. We discussed issues regarding benchmarking with Dr. Lee.  Since our design will not be comparable to commercially available processors, benchmarking will not be very applicable in our design.
3. The shifter design was modified in order to do arithmetic and logical shift with the same shifter unit.
4. Worked on conditional codes for the ALU operations.

Next Week:

1. By next week we will have the ALU coded and tested.
2. We will add all clock gating signals to the control unit of the processor and also will do the ALU control unit.
3. Due to some recent changes, we will recode instruction fetch unit.

Team Report #8 (1/19/04):

Last Week:

1. Worked on the adder, shifter, Hazard detection unit and Forward Unit.

2. Started the final report.

Next Week:

1.  Will work on unsigned and conditional codes, namely overflow and carryout.

2. Will look into clock gating.

3.  Will work on Modify shifter.

4. Look into benchmarking.

Team Report #7 (1/1/04):

Last Week:

1. Worked on the adder and shifter design for a ALU and the integration of all the components of the ALU.
2. Did research on pipelining, clock-gating, and control module design.
3. Wrote the VHDL code for most of the ALU.

Next Week:

1. Will work on the final report.
2. Start the final presentation.
3. Will start testing our design.
    

Team Report #6  (12/15/03):

Last Week:

1. Performed research to see if inclusion of sleep mode is possible in our process design.
2. Came up with the VHDL code for multiplier.
3. Worked on shifter for ALU.

Next Week:

1. Will work on Ram Design and register file design.
2. Do research on the efficient ALU.
3. Will work on the adder and shifter part of the ALU.