Overview of Design
Phase one of the project will be to identify time consuming code programmed into the DSP board and migrate it to an field programmable gate array (FPGA). Because of the nature of computers and dsps, operations are currently being executed sequentially. This creates a bottleneck, in that the computer or dsp must execute instruction 'i' before it can execute instruction 'i+1'. If instructions don't depend on each other, they could be executed in parallel, instead of sequentially. We intend to move these instructions to fpga, and have them executed at the same time, while sending their output back to the main dsp board. Also, we will try to make operations independent, so that we can then execute them in parallel.
Phase two of the project will be to use the modem to acquire, transmit and receive sound and picture data.
Sponsoring Organization: University of Connecticut, School of Engineering
Adviser: Shengli Zhou
Email: shengli@engr.uconn.edu