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John Chandy
Assistant Professor
On faculty since 2002University of Connecticut
Electrical & Computer Engineering
371 Fairfield Way; U-2157
Storrs, Connecticut 06269-2157 USAOffice: ITE Building 437
Phone: (860) 486-5047
Fax: (860) 486-2447
E-Mail:john.chandy@uconn.eduEducation:
Ph.D Electrical Engineering, University of Illinois, 1996
M.S. Electrical Engineering, University of Illinois, 1993
S.B. Electrical Engineering, Massachusetts Institute of Technology, 1989Research Interests:
Clustered network storage and distributed file systems, parallel algorithms and distributed system architectures, reconfigurable computingMemberships:
Institute of Electrical and Electronics Engineers (IEEE)
Association for Computing Machinery (ACM)Recent Publications:
Archival Technical Journal Publications:"A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement," (with P. Banerjee), Journal of Parallel and Distributed Computing, vol. 57, no. 1, pp. 64-90, April 1999.
"An Evaluation of Parallel Simulated Strategies with Application to Standard Cell Placement", (with S. Kim, B. Ramkumar, S. Parkes, and P. Banerjee), IEEE Transactions on Computer-Aided Design, vol. 16, no. 4, pp. 398-410, April 1997.
Conference Proceedings & Other Publications:
" Trace Based Analysis of File System Effects on Disk I/O, " (with S. Narayan), Proceedings of the International Symposium on Performance Evaluation of Computer and Telecommunication Systems, July, 2004.
" A Signature Match Processor Architecture for Network Intrusion Detection, " (with J. Singaraju and L. Bu), Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April, 2005.
" A Quorum Based Content Delivery Architecture, " (with M. Kapralos), Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, June, 2005.
"A Scalable Architecture for Clustered Network Attached Storage," (with J.D. Bright), Proceedings of the IEEE Mass Storage Systems and Technologies Symposium, San Diego, April 2003.
"WADE: A Web-based Automated Parallel CAD Environment," (with D.R. Chakrabarti, P.G. Joisha, D. Krishnaswamy, V. Krishnaswamy, and P. Banerjee), Proceedings of HiPC, International Conference on High Performance Computing, Chennai, India, December 1998.
"A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement," (with P. Banerjee), Proceedings of the International Conference on Computer Design, Austin, October 1997.
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" Techniques for Hardware Assisted Storage Network Protocol Processing," University of Connecticut Research Foundation, June 1, 2004-May 31, 2005.
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Member, Program Committee, International Conference on Parallel and Distributed Processing Techniques and Applications, 2005.
Member, Program Committee, IASTED International Conference on Advances in Computer Science and Technology.
Presentations:
" Design and Implementation of a Clustered Network Storage System, " Cochin University of Science and Technology, Cochin, Kerala, India, July 15, 2004.
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