Mohammad Tehranipoor Assistant Professor On faculty since 2006 University of Connecticut Electrical & Computer Engineering 371 Fairfield Way; U-2157 Storrs, CT 06269-2157 USA Office: ITE Building 441 Phone: (860) 486-3471 Fax: (860) 486-2447 E-Mail: tehrani@engr.uconn.edu Personal Page: http://www.engr.uconn.edu/~tehrani

Education:
Ph.D., Electrical Engineering, University of Texas at Dallas, 2004
M.S., Electrical Engineering, University of Tehran, 2000
B.S. Electrical Engineering, Tehran Polytechnic University, Tehran, 1997

Memberships:
ACM-SIGDA
IEEE - The Institute of Electrical and Electronics Engineers

Conference Proceedings
Professional Activities

Recent Publications:
Archival Technical Journal Publications:

 "Low-Transition Test Pattern Generation for BIST-Based Applications," (with M. Nourani, and N. Ahmed), IEEE Transactions on Computers, 2006.

 "Improving Quality of Transition Delay Test Using Hybrid Scan-Based Technique," (with N. Ahmed), IEEE Design and Test of Computers, 2006.

"Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers," (with N. Ahmed, C.P. Ravikumar and K. Butler), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), 2006.

"Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based NanoFabrics," (with R. M.P. Rad), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), 2006

"Test Chip Results Investigating Defect Sensitivity of Quiescent Signal Analysis: a Multiple Supply Pad I_DDQ Method," (with D. Acharyya, A. Singh, C. Patel and J. Plusquellic), IEEE Design and Test of Computers, 2006.

"Nine-Coded Compression Technique for Testing Embedded Cores in SoCs," (with M. Nourani and K. Chakrabarty), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 13, no. 6, pp. 719-731, June 2005.

"RL-Huffman Encoding for Test Compression and Power Reduction in Scan Application," (with M. Nourani), ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 10, no. 1, pp. 91-115, Jan. 2005.

"Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture," (with N. Ahmed and M. Nourani), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), vol. 23, issue 5, pp. 800-811, May 2004.

"A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores," (with S. M. Fakhraie, Z. Navabi and M. R. Movahedin), Journal of Electronic Testing: Theory and Applications (JETTA), vol. 20, pp. 155-168, April 2004.

Conference Proceedings & Other Publications:

"A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-Drop Effects," (with N. Ahmedand V. Jayaram, ), in proc. of Int. Conf. on Computer-Aided Design (ICCAD'06), 2006.

"A Hybrid FPGA Using Nanoscale Cluster and CMOS Scale Routing," (with R. M. Rad), in proc. of Design Automation Conference (DAC'06), 2006.

"Timing-Based Delay Test for Screening Small Delay Defects," (N. Ahmed and V. Jayaram, ), in proc. of Design Automation Conference (DAC'06), 2006.

"A Reconfiguration-based Defect Tolerance Method for Nanosclae Devices," (with R. M. Rad), in proc. of Int. Symposium on Defect and Fault Tolerance of VLSI Systems (DFT'06), 2006.

 "SCT: An Approach for Testing and Configuring Nanoscale Devices," (with R. M. Rad), in proc. of IEEE VLSI Test Symposium (VTS'06), 2006.

"A Low-Cost Solution for Protecting IPs Against Side-Channel Scan-Based Attacks," (with J. Lee and J. Plusquellic), in proc. of IEEE VLSI Test Symposium (VTS'06), 2006.

"A Novel Framework for Functionally Untestable Transition Fault Avoidance during ATPG," (with J. Lee, N. Ahmed, V. Jayaram and J. Plusquellic, ), IEEE North Atlantic Test Workshop (NATW'06), 2006.

"Partial Gating Optimization for Power Reduction During Test Application," (with M. ElShoukry and C.P. Ravikumar ), in proc. of IEEE 14^th Asian Test Symposium (ATS'05), 2005.

"Low Transition LFSR for BIST-Based Applications," (with M. Nourani and N. Ahmed), in proc. of IEEE 14^th Asian Test Symposium (ATS'05), 2005.

"Securing Scan Design Using Lock & Key Technique," (with J. Lee, C. Patel and J. Plusquellic), in proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.

"Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique," (with N. Ahmed), in proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.

 "Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure," in proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.

"Enhanced Launch-off-Capture Transition Fault Testing," (with N. Ahmed and C.P. Ravikumar), in proc. of IEEE International Test Conf. (ITC'05), 2005.

"Pattern Generation and Estimation for Power Supply Noise Analysis," (with M. Nourani and N. Ahmed), in proc. IEEE VLSI Test Symposium (VTS'05), pp. 439-444, 2005.

"At-Speed Transition Fault Testing With Low Speed Scan Enable," (with N. Ahmed, C.P. Ravikumar and J. Plusquellic), in proc. IEEE VLSI Test Symposium (VTS'05), pp. 42-47, 2005.

"Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression," (with M. Nourani and K. Chakrabarty), in proc. IEEE/ACM Design, Automation and Test in Europe (DATE'04), Paris, France, vol. 2, pp. 1284-1289, 2004.

"Testing SoC Interconnects for Signal Integrity Using Boundary Scan," (with N. Ahmed and M. Nourani), in proc. IEEE VLSI Test Symposium (VTS'03), Napa, CA, pp. 158-163, 2003.

"Extending JTAG for Testing Signal Integrity in SoCs," (with N. Ahmed and M. Nourani), in proc. IEEE/ACM Design, Automation and Test in Europe (DATE'03), Messe Munich, Germany, pp. 218-223, 2003.

"Multiple Transition Model and Enhanced Boundary Scan Architecure to Test Interconnects for Signal Integrity," (with N. Ahmed and M. Nourani), in proc. IEEE International Conference on Computer Design (ICCD'03), San-Jose, pp. 554-559, CA, 2003.

Professional Activities:

Guest Editor, Journal of Electronic Testing: Theory and Applications (JETTA)

Guest Editor, IEEE Design and Test of Computers

Program Committee:

    IEEE North Atlantic Test Workshop

    Int. Symp. on Defect and Fault Tolerance

    IEEE Defect-Based Testing Workshop

    Int. Design and Test Workshop

Panel Co-Organizer, IEEE VLSI Test Symposium (VTS), 2006

Session Chair:

    ITC06, DBT05, NATW05 and 06, ATS05

Reviewer:

    NSF, TCAD, TVLSI, TC, TODAES, IBM Journal, ITC, VTS, DAC, ICCAD