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Lei Wang
Assistant Professor
On faculty since 2004University of Connecticut
Electrical & Computer Engineering
371 Fairchild Way; U-2157
Storrs, Connecticut 06269-2157 USAOffice: ITE Building 455
Phone: (860) 486-3066
Fax: (860) 486-2447
E-Mail: leiwang@engr.uconn.edu
WEB Page:http://www.engr.uconn.edu/~leiwangEducation:
PhD, University of Illinois at Urbana-Champaign, 2001
MS, Tsinghua University, China, 1996
BS, Tsinghua University, China, 1992Research Interests:
Computer microarchitecture and implementation, Design methodologies for nanoscale ASIC/SOC, Performance limits of nanoscale integrated systems, VLSI signal processing algorithms and architectures.Memberships:
Institute of Electrical and Electronics Engineers (IEEE)
Recent Publications
Active Research Projects
Professional ActivitiesArchival Technical Journal Publications:
"Low-power MIMO signal processing," (with N. R. Shanbhag), IEEE Transactions on VLSI Systems, vol. 11, pp. 434-445, June 2003.
"Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise," (with N. R. Shanbhag), IEEE Transactions on VLSI Systems, vol. 11, pp. 254-269, April 2003.
"Low-power filtering via adaptive error-cancellation," (with N. R. Shanbhag), IEEE Transactions on Signal Processing, vol. 51, pp. 575-583, February 2003.
"An energy-efficient noise-tolerant dynamic circuit technique," (with N. R. Shanbhag), IEEE Transactions on Circuits and Systems, Part II, vol. 47, pp. 1300-1306, November 2000
Conference Proceedings & Other Publications:
" The Multi-Threaded, Parity Protected, 128 Word Register Files on a Dual-Core Itanium Family Processor, " (with E. Fetzer and J. Jones), Proceedings of the IEEE International Solid-State Circuits Conference, February, 2005.
" Nanotechnological Solutions to Emerging Challenges in Computer Microarchitecture, " Proceedings of the 14th Connecticut Symposium on Microelectronics and Optoelectronics, March, 2005.
" An Energy-Efficient Skew Compensation Technique for High-Speed Skew-Sensitive Signaling, " IEEE International Symposium on Circuits and Systems, May, 2005.
" Low-power AEC-based MIMO signal processing for Gigabit Ethernet 1000Base-T transceivers, " (with N. R. Shanbhag), Proceedings of the International Symposium on Low-Power Electronics and Design, pp. 334-339, August 2001.
"Adaptive error-cancellation for low-power digital filtering," (with N. R. Shanbhag), Proceedings of the 34th Asilomar Conference on Signals, Systems and Computers, pp. 1702-1706, October 2000.
"Low-power signal processing via error-cancellation," (with N. R. Shanbhag), Proceedings of the IEEE Workshop on Signal Processing Systems, pp. 553-562, October 2000.
"An energy-efficient leakage-tolerant dynamic circuit technique," (with R. Krishnamurthy, K. Soumyanath, and N. R. Shanbhag), Proceedings of the 13th IEEE International ASIC/SOC Conference, pp. 221-225, September 2000.
"Energy-efficiency bounds for noise-tolerant dynamic circuits," (with N. R. Shanbhag), Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 273-276, May 2000.
"Noise-tolerant dynamic circuit design," (with N. R. Shanbhag), Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 549-552, May 1999.
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" Adaptive Design Framework for Mission-Specific Integrated Microsystems, " UConn Large Grant Faculty Research, January 1, 2005-December 31, 2006.
Professional Activities:
TPC Member for the 16th ACM Great Lakes Symposium on VLSI (GLSVLSI 2006)TPC Member for the 7th International Symposium on Quality Electronic Design (ISQED 2006)
Reviewer for:
IEEE Transactions on Circuits and Systems
IEEE Transactions on Signal Processing
IEEE Transactions on VLSI Systems
Presentation:
" Nanotechnological Solutions to Emerging Challenges in Computer Microarchitecture, "14th Connecticut Symposium on Microelectronics and Optoelectronics, Yale University, New Haven, CT, March, 2005.
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" Circuit and Method for Improving Noise Tolerance in Multi-Threaded Memory Circuits, " Patent # 6,850,093, February 1, 2005.
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