Cadence Design Tools have been installed on the Linux workstations in ITEB C27.
ECE 3421 VLSI Design and Simulation
Design of MOS transistors, including short channel effects in sub-micron devices; scaling laws; design rules. Layout of NMOS and CMOS logic gates; power-delay calculations. Design of static and/or dynamic memories. Laboratory emphasizes schematic capture, simulation, timing analysis and testing; layout of custom IC's; use of VHDL.
ECE6421 Advanced VLSI Design (Graduate Level)
CMOS devices and manufacturing technology. Digital CMOS logic gate and their layout. Combinational and sequencial circuit design. Various digital design styles and architectures. Noise sources and signal integrity in digital design. Arithmetic circuits, memories and other novel circuits. Design techniques for dynamic and static power reduction. Power supply issues, interconnect analysis, clocking and synchronization. CAD tools for layout, extraction and simulation. Verilog-HDL languages and Cadence design automation tools.
Research Labs Using Cadence Design Tools
Micro/Optoelectronics Research Laboratory,
F.C. Jain.This laboratory is equipped with CVD reactors for Ge and Si
growth; MOCVD reactors for ZnS, ZnMgSSe, ZnZnCdSe growth (including a quantum
dot growth setup) and PL and X-Ray setups for characterization; a
photolithographic clean room to process lasers, transistors and integrated
circuits; measurement setups to characterize lasers, modulators, and filters;
and dedicated workstations for computer-aided design (Cadence Tools) and
simulation. Current research is focused on 1.55 micron MQW optical modulators,
tunable lasers, SiGe FETs, terahertz MODFETs and quatum interference
transistors, quantum dot-based nanophosphors and lasers.