{"id":2,"date":"2017-01-13T21:43:56","date_gmt":"2017-01-13T21:43:56","guid":{"rendered":"http:\/\/www.ee.uconn.edu\/john-chandy\/?page_id=2"},"modified":"2022-01-06T19:00:16","modified_gmt":"2022-01-06T19:00:16","slug":"publications","status":"publish","type":"page","link":"https:\/\/www.ee.uconn.edu\/john-chandy\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"

List publications By Topic<\/a><\/b><\/p>\n

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Publication List<\/h3>\n
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Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic<\/strong><\/a>
\nF. Jain<\/a>, R. H. Gudlavalleti, R. Mays, B. Saman, J. Chandy<\/a>, and Evan Heller
\nNanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications<\/i>, pp. 187-197, November 2021.<\/p>\n

3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs<\/strong><\/a>
\nB. Saman, R. H. Gudlavalleti, R. R. Mays, J. Chandy<\/a>, Evan Heller and F. Jain<\/a>
\nNanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications<\/i>, pp. 139-150, November 2021.<\/p>\n

Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs<\/strong><\/a>
\nH. Salama, B. Saman, R. Gudlavalleti, R. Mays,\u00a0E. Heller, J. Chandy<\/a>,\u00a0and F. Jain<\/a>
\nNanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications<\/i>, pp. 129-138, November 2021.<\/p>\n

3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL)<\/strong><\/a>
\nF. Jain<\/a>, B. Saman, R. H. Gudlavalleti, R. Mays, J. Chandy<\/a>, and Evan Heller
\nNanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications<\/i>, pp. 103-118, November 2021.<\/p>\n

A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array<\/strong><\/a>
\nR. H. Gudlavalleti, B. Saman, R. Mays, H. Salama, Evan\u00a0Heller, J. Chandy<\/a>,\u00a0and F. Jain<\/a>,
\nNanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications<\/i>, pp. 83-92, November 2021.<\/p>\n

Zero Trust for Hardware Supply Chains: Challenges in Application of Zero Trust Principles to Hardware<\/strong><\/a>
\nD. DiMase, Z. A. Collier, J. Muldavin, J. A. Chandy<\/a>, D. Davidson, D. Doran, U. Guin<\/a>, J. Hallman, J. Heebink, E. Hall, A. R. Shaffer
\nNational Defense Industrial Association White Paper, October 2021.<\/p>\n

Low-Threshold II\u2013VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic<\/strong><\/a>
\nF. Jain<\/a>, B. Saman, R. Gudlavalleti, R. Mays, J. Chandy<\/a> and E. Heller
\nJournal of Electronic Materials, <\/em>March 2021.<\/p>\n

Bit2RNG: Leveraging Bad-page Initialized Table with Bit-error Insertion for True Random Number Generation in Commodity Flash Memory<\/strong><\/a>
\nW. Yan<\/a> H. Zhu, Z. Yu, F. Tehranipoor, J. Chandy<\/a>, N. Zhang, and\u00a0X. Zhang
\nProceedings of IEEE International Symposium on Hardware Oriented Security and Trust<\/em>, December 2020.<\/p>\n

Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations<\/strong><\/a>
\nR. H. Gudlavalleti, B. Saman, R. Mays, M. Lingalugari, E. Heller, J. Chandy<\/a>, and F. Jain<\/a>
\nNanotechnology for Electronics, Photonics, Biosensors, and Emerging Technologies<\/i>, pp. 135-142, September 2020.<\/p>\n

Simulation of Stacked Quantum Dot Channels SWS-FET Using Multi-FET ABM Modeling<\/strong><\/a>
\nH. Salama, B. Saman, R. H. Gudlavalleti, P-Y. Chan, R. Mays, B. Khan, E. Heller, J. Chandy<\/a>, and F. Jain<\/a>
\nNanotechnology for Electronics, Photonics, Biosensors, and Emerging Technologies<\/i>, pp. 129-133, September 2020.<\/p>\n

Exploring the Coverage of Existing Hardware Vulnerabilities in Community Standards<\/strong><\/a>
\nPaul A. Wortman<\/a>, Fatemeh Tehranipoor<\/a> and John A. Chandy<\/a>.
\nin Proceedings of Silicon Valley Cybersecurity Conference<\/i>. pp. 87-97. December 2020.<\/p>\n

FLASH: FPGA Locality Associated Secure Hash for Nearest Neighbor Search and Clustering Application<\/strong><\/a>
\nW. Yan<\/a>, F. Tehranipoor, X. Zhang, and J. Chandy<\/a>
\nProceedings of International Conference on Field-Programmable Logic and Applications, <\/em>pp. 249-253, September 2020.<\/p>\n

A Holistic Approach to Cyber Physical Systems Security and Resilience<\/strong><\/a>
\nD. DiMase, Z.A. Collier, John Chandy<\/a>, B.S. Cohen, G. D\u2019Anna, H. Dunlap, J. Hallman, J.\u00a0Mandelbaum, J. Ritchie, and L. Vessels
\nIEEE Systems Security Symposium<\/em>, pp. 1-8, July 2020,<\/p>\n

A Trace-Based Study of SMB Network File System Workloads in an Academic Enterprise<\/strong><\/a>
\nPaul A. Wortman<\/a> and John.A. Chandy<\/a>
\nProceedings of International Symposium on Performance Evaluation of Computer and Telecommunication Systems<\/em>, July 2020.<\/p>\n

SMART: security model adversarial risk-based tool for systems security design evaluation<\/strong><\/a>
\nP. A. Wortman<\/a> and John A. Chandy<\/a>
\nin Journal of Cybersecurity<\/i>. vol. 6, no. 1. Feb. 2020.<\/p>\n

Embedded Systems Authentication and Encryption using Strong PUF Modeling<\/strong><\/a>
\nS. Enamul Quadir<\/a> and John.A. Chandy<\/a>
\nInternational Conference on Consumer Electronics, <\/em>Jan. 2020.<\/p>\n

Key Generation for Hardware Obfuscation using Strong PUFs<\/strong><\/a>
\nS. Enamul Quadir<\/a> and John.A. Chandy<\/a>
\nCryptography, <\/em>vol. 3, no. 2. July 2019.<\/p>\n

HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion<\/b>
\n<\/a>Michael Kapralos<\/a> and <\/a>John A. Chandy<\/a>
\nin Proceedings of the ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays<\/i>, February 2019.<\/a><\/p>\n

Eight-bit ADC using non-volatile flash memory<\/b><\/a>
\nS. Karmakar<\/a>, J. A. Chandy<\/a>, and F.C. Jain<\/a>.
\nIET Circuits, Devices & Systems,<\/i> 13(1):98-102. Jan. 2019.<\/p>\n

Engineering for Vehicle Cybersecurity<\/strong><\/a>
\nD. DiMase, Z.A. Collier, J. A. Chandy<\/a>, P. Bronn, K. Heffner and S. Walters.
\nin Cybersecurity for Commercial Vehicles<\/i> SAE. 2019.<\/p>\n

P2M-based security model: security enhancement using combined PUF and PRNG models for authenticating consumer electronic devices<\/strong><\/a>
\nPaul Wortman<\/a>, Wei Yan<\/a>, John A. Chandy<\/a>, and Fatemeh Tehranipoor<\/a> in IET Computers and Digital Techniques<\/i>, vol. 12, no. 66, pp. 289-296, November 2018.<\/p>\n

Low Pass Filter PUF: Authentication of Printed Circuit Boards Based on Resistor and Capacitor Variations<\/strong><\/a>
\nS. Enamul Quadir<\/a> and John A. Chandy<\/a>.
\nInternational Journal of High Speed Electronics and Systems,<\/i> vol 27. Sept.\/Dec. 2018.<\/p>\n

Phase Calibrated Ring Oscillator PUF Design and Application<\/strong><\/a>
\nWei Yan<\/a> and John Chandy<\/a>
\nComputers,<\/i> vol 7. July 2018.<\/p>\n

DVFT: A Lightweight Solution for Power Supply Noise-based TRNG using Dynamic Voltage Feedback Tuning System<\/strong><\/a>
\nF. Tehranipoor<\/a>, P. Wortman<\/a>, N. Karimian<\/a>, W. Yan<\/a>, and J. A. Chandy<\/a>
\nin IEEE Transactions on VLSI Systems<\/i>, vol. 26, no. 6, pp. 1084-1097, June 2018<\/p>\n

An Adversarial Risk-based Approach for Network Architecture Security Modeling and Design<\/strong><\/a>
\nP. A. Wortman<\/a> and John A. Chandy<\/a>
\nin Proceedings of Cyber Security 2018<\/i>. Jun 2018.<\/p>\n

Error Tolerant ASCA on FPGA<\/strong><\/a>
\nC. Ma<\/a>, and J,A. Chandy<\/a>
\nInternational Conference on Cloud Computing and Security<\/em>, pp. 563-572, June 2018<\/p>\n

Framework for Design Exploration of Secure Embedded System Development<\/strong><\/a>
\nPaul A. Wortman<\/a>, Fatemeh Tehranipoor<\/a> and John A. Chandy<\/a>.
\nin Proceedings of Conference on Systems Engineering Research<\/i>. May 2018.<\/p>\n

Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Ge Quantum Dot Channel for Faster Erasing<\/strong><\/a>
\nM. Lingalugari, E. Heller, B. Parthasarathy, J. Chandy<\/a>, and F. Jain<\/a>
\nin International Journal of High Speed Electronics and Systems<\/i>, vol. 27, issue 01, March\/June 2018.<\/p>\n

Circuits and Simulation of Quaternary SRAM Using Quantum Dot Channel Field Effect Transistors (QDC-FETs)<\/strong><\/a>
\nB. Saman, J. Kundo, J. Chandy<\/a>, and F.C. Jain<\/a>
\nin International Journal of High Speed Electronics and Systems<\/i>, vol. 27, issue 01, March\/June 2018<\/p>\n

An Overview of DRAM-Based Security Primitives<\/strong><\/a>
\nN.A. Anagnostopoulos<\/a>, S. Katzenbeisser, J. Chandy<\/a>, and F. Tehranipoor<\/a>
\nin Cryptography <\/i>, vol. 2(2), no. 7, March 2018<\/p>\n

QD floating gate NVRAM using QD channel for faster erasing<\/strong><\/a>
\nM. Lingalugari, P-Y. Chan, E.K. Heller, J. Chandy<\/a>, and F.C. Jain<\/a>
\nin Electronics Letters<\/i>, vol. 54, no. 1, pp. 36-37. January 2018<\/p>\n

Low-cost Authentication Paradigm for Consumer Electronics Within the Internet of Wearable Fitness Tracking Applications<\/strong><\/a>
\nFatemeh Tehranipoor<\/a>, Nima Karimian<\/a>, Paul A. Wortman<\/a>, and John A. Chandy<\/a>
\nin Proceedings of IEEE International Conference on Consumer Electronics<\/i>, January 2018.<\/p>\n

Exploring Methods of Authentication for the Internet of Things<\/strong><\/a>
\nF. Tehranipoor<\/a>, N. Karimian<\/a>, P.A. Wortman<\/a>, A. Haque, J. Fahrny, and J. A. Chandy<\/a>
\nin Internet of Things: Challenges, Advances, and Applications<\/i>, ed. By Q.F. Hassan, A.u.R. Khan, and S.A. Madani, 2018.<\/p>\n

Influence of Error and Hamming Weights on ASCA<\/strong><\/a>
\nC. Ma<\/a>, J. Chandy<\/a>, L. Michel<\/a>, F. Liu and W. Cruz.
\nin Proceedings of International Conference on Information Security and Cryptology<\/i>. November 2017.<\/p>\n

Phase calibrated ring oscillator PUF design and implementation on FPGAs<\/strong><\/a>
\nWei Yan<\/a>, Chenglu Jin<\/a>, Fatemeh Tehranipoor<\/a>, and John A. Chandy<\/a>
\nin Proceedings of International Conference on Field-Programmable Logic and Applications<\/i>, Ghent, Belgium, Sept. 2017.<\/p>\n

PUF-based Fuzzy Authentication without Error Correcting Codes<\/strong><\/a>
\nWei Yan<\/a>, Fatemeh Tehranipoor<\/a>, and John A. Chandy<\/a>
\nin IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems<\/i>, vol. 36, no. 9, pp. 1445-1457, Sept. 2017.<\/p>\n

Multi-bit NVRAMs Using Quantum Dot Gate Access Channel<\/strong><\/a>
\nM. Lingalugari, P-Y. Chan, J. Chandy<\/a>, E.K. Heller, and F.C. Jain<\/a>
\nin International Journal of High Speed Electronics and Systems<\/i>, vol. 26, no. 3, September 2017<\/p>\n

Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation<\/strong><\/a>
\nB. Saman, P. Gogna, E.-S. Hasaneen, J. Chandy<\/a>, E.K. Heller, and F.C. Jain<\/a>
\nin International Journal of High Speed Electronics and Systems<\/i>, vol. 26, no. 3, September 2017<\/p>\n

DRNG: DRAM-based random number generation using its startup value behavior<\/strong><\/a>
\nCharles Eckert, Fatemeh Tehranipoor<\/a>, and John A. Chandy<\/a>
\nin Proceedings of IEEE International Midwest Symposium on Circuits and Systems<\/i>, Boston, MA, August 2017.<\/p>\n

Insights into the Potential Usage of the Initial Values of DRAM Arrays of Commercial Off-the-Shelf Devices for Security Applications<\/strong><\/a>
\nN. A. Anagnostopoulos, Andre Schaller, Yufan Fan, Wenjie Xiong, Fatemeh Tehranipoor<\/a>, Tolga Arul, Sebastian Gabmeyer, Jakub Szefer, John A. Chandy<\/a> and Stefan Katzenbeisser.
\nin 2017 Crypto-Day Proceedings<\/i>. Jun 2017.<\/p>\n

A design flow with integrated verification of requirements and faults in safety-critical systems<\/strong><\/a>
\nWei Yan<\/a>, Daniel Fontaine, John A. Chandy<\/a>, and Laurent Michel<\/a>
\nin Proceedings of System of Systems Engineering Conference<\/i>, Hawaii, June 2017.<\/p>\n

Algebraic Side-Channel Attack on Twofish<\/strong><\/a>
\nChujiao Ma<\/a>, John A. Chandy<\/a>, and Zhijie Shi
\nin Journal of Internet Services and Information Security<\/i>, vol. 7, no. 2, pp. 32-43, May 2017.<\/p>\n

Investigation of DRAM PUFs reliability under device accelerated aging effects<\/strong><\/a>
\nFatemeh Tehranipoor<\/a>, Nima Karimian<\/a>, Wei Yan<\/a>, and John A. Chandy<\/a>
\nin Proceedings of IEEE International Symposium on Circuits and Systems<\/i>, May 2017.<\/p>\n

CHASE Survey of Technology Needs<\/b>
\nS. Enamul Quadir<\/a>, Daniel DiMase and John A. Chandy<\/a>
\nin GOMACTech<\/i>. March 2017.<\/p>\n

DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication<\/strong><\/a>
\nFatemeh Tehranipoor<\/a>, Nima Karimian<\/a>, Wei Yan<\/a>, and John A. Chandy<\/a>
\nin IEEE Transactions on VLSI Systems<\/i>, vol. 25, no. 3, pp. 1085-1097, March 2017.<\/p>\n

Proposing a modeling framework for minimizing security vulnerabilities in IoT systems in the healthcare domain<\/strong><\/a>
\nPaul A. Wortman<\/a>, Fatemeh Tehranipoor<\/a>, Nima Karimian<\/a> and John A. Chandy<\/a>
\nin Proceedings of IEEE EMBS International Conference on Biomedical and Health Informatics<\/i>, February 2017.<\/p>\n

A Study of Power Supply Variation as a Source of Random Noise<\/strong><\/a>
\nFatemeh Tehranipoor<\/a>, Nima Karimian<\/a>, Wei Yan<\/a>, and John A. Chandy<\/a>
\nin Proceedings of IEEE International Conference on VLSI Design<\/i>, January 2017.<\/p>\n

Adding Data Analytics Capabilities to Scaled-out Object Store<\/strong><\/a>
\nCengiz Karakoyunlu<\/a>, John A. Chandy<\/a>, and Alma Riska in Journal of Systems and Software<\/i>, vol. 121, pp. 16-27, November 2016.<\/p>\n

Quantum Dot Channel (QDC) FETs with Wraparound II-VI Gate Insulators: Numerical Simulations<\/strong><\/a>
\nFaquir Jain<\/a>, Murali Lingalugari, Jun Kundo, Pial Mirdha, Ernesto Suarez, John A. Chandy<\/a>, and Evan Heller in Journal of Electronic Materials<\/i>, vol. 45, no. 11, pp. 5663-5670, November 2016.<\/p>\n

A Survey on Chip to System Reverse Engineering<\/strong><\/a>
\nS.E. Quadir<\/a>, J. Chen, D. Forte, N. Asadizanjani, S. Shahbazmohamadi, L. Wang, John Chandy<\/a>, and M. Tehranipoor<\/a> in ACM Journal on Emerging Technologies in Computing Systems<\/i>, vol. 13, no. 1, article 6, May 2016<\/p>\n

Robust hardware true random number generators using DRAM remanence effects<\/strong><\/a>
\nFatemeh Tehranipoor<\/a>, Wei Yan<\/a>, and John A. Chandy<\/a>
\nin Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust, <\/i>McLean, VA, pp. 79-84, May 2016.<\/p>\n

Exploiting User Metadata for Energy-Aware Node Allocation in a Cloud Storage System<\/strong><\/a>
\nCengiz Karakoyunlu<\/a> and John A. Chandy<\/a>
\nin Journal of Computer and System Sciences<\/i>, vol. 82, no. 2, pp. 282-309, March 2016.<\/p>\n

A Novel Way to Authenticate Untrusted Integrated Circuits<\/strong><\/a>
\nWei Yan<\/a>, Fatemeh Tehranipoor<\/a>, and John A. Chandy<\/a>
\nin Proceedings of International Conference on Computer-Aided Design, <\/i>Austin, TX, pp. 132-138, November 2015.<\/p>\n

Leveraging Checkpoint\/Restore to Optimize Utilization of Cloud Compute Resources<\/strong><\/a>
\nRohit Mehta and John A. Chandy<\/a>
\nin Proceedings of IEEE Workshop on Cloud-Based Networks and Applications<\/i>Clearwater Beach, FL, pp. 714-721, October 2015.<\/p>\n

Novel Multiplexer Design Using Multi-State Spatial Wavefunction-Switched (SWS) FETs<\/strong><\/a>
\nPial Mirdha, Murali Lingalugari, Evan K. Heller, John
\nA. Chandy<\/a>, and Faquir C. Jain<\/a>
\nin International Journal of High Speed Electronics and Systems<\/i>, vol. 24, issue 03, no. 04, Sept.\/Dec. 2015.<\/p>\n

Si and InGaAs Spatial Wavefunction-Switched (SWS) FETs with II\u2013VI Gate Insulators: An Approach to the Design and Integration of Two-Bit SRAMs and Binary CMOS Logic<\/strong><\/a>
\nFaquir Jain<\/a>, Pik-Yiu Chan, Murali Lingalugari, Jun Kondo, Ernesto Suarez, Pawan Gogna, John Chandy<\/a>, and Evan Heller in Journal of Electronic Materials<\/i>, vol. 44, no. 9, pp. 3109-3115, September 2015.<\/p>\n

Hardware Hacking: An Approach to Trustable Computing Systems Security Education<\/b>
\nJohn A. Chandy<\/a>, Zhijie Shi, Mohammad Tehranipoor<\/a>, Megan Welsh, Chujiao Ma<\/a>, Qihang Shi, and Ujjwal Guin<\/a>
\nin Colloquium for Information Systems Security Education, <\/i>Las Vegas, NV, June 2015.<\/p>\n

DRAM based Intrinsic Physical Unclonable Functions for System Level Security<\/strong><\/a>
\nFatemeh Tehranipoor<\/a>, Nima Karimian<\/a>, Kan Xiao, and John A. Chandy<\/a>
\nin Proceedings of ACM Great Lakes Symposium on VLSI,<\/i>Pittsburgh, PA,pp. 15-20, May 2015.<\/p>\n

Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs<\/strong><\/a>
\nSupriya Karmakar<\/a>, John A. Chandy<\/a>, and Faquir C. Jain<\/a> in IEEE Transactions on Very Large Scale Integration (VLSI) Systems<\/i>, vol. 23, no. 4, pp. 609-618, April 2015.<\/p>\n

Active Storage Networks: Using Embedded Computation in the Network Switch for Cluster Data Processing<\/strong><\/a>
\nJanardhan Singaraju<\/a>, Ajithkumar Thamarakuzhi<\/a> and John A. Chandy<\/a>
\nin Future Generation Computer Systems<\/i>, vol. 45, pp. 149-160, April 2015.<\/p>\n

Using an Object-Based Active Storage Framework to Improve Parallel Storage<\/strong><\/a>
\nCengiz Karakoyunlu<\/a>, Michael Runde<\/a>, and John A. Chandy<\/a>
\nin Proceedings of Workshop on Interfaces and Architectures for Scientific Data Storage <\/i>Minneapolis, MN, Sept. 2014.<\/p>\n

Creating a programmable object storage stack<\/strong><\/a>
\nOrko Momin<\/a>, Cengiz Karakoyunlu<\/a>, Michael T. Runde<\/a>, and John A. Chandy<\/a>
\nin Proceedings of the Programmable File Systems Workshop <\/i>, Vancouver, CANADA, June 2014.<\/p>\n

Ge-ZnSSe Spatial Wavefunction Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic<\/strong><\/a>
\nPawan Gogna, Ernesto Suarez, Murali Lingalugari, John Chandy<\/a>, Evan Heller, E.-S. Hasaneen, and Faquir C. Jain<\/a>
\nin Journal of Electronic Materials <\/i>, vol. 42, no. 11, pp. 3337-3343, November 2013.<\/p>\n

Four-State Sub-12-nm FETs Employing Lattice-Matched II\u2013VI Barrier Layers<\/strong><\/a>
\nFaquir Jain<\/a>, Pik-Yiu Chan, Ernesto Suarez, Murali Lingalugari, Jun Kondo, Pawan Gogna, Barry Miller, John Chandy<\/a>, and Evan Heller
\nin Journal of Electronic Materials<\/i>, vol. 42, no. 11, pp. 3191-3202, November 2013.<\/p>\n

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators<\/strong><\/a>
\nMurali Lingalugari, Kavitha Baskar, Pik-Yiu Chan, P. Dufilie, Ernesto Suarez, John Chandy<\/a>, Evan Heller, E.-S. Hasaneen, and Faquir C. Jain<\/a>
\nin Journal of Electronic Materials<\/i>, vol. 42, no. 11, pp. 3156-3163, November 2013<\/p>\n

An object interface storage node for clustered file systems<\/strong><\/a>
\nOrko Momin<\/a> and John A. Chandy<\/a>
\nin Proceedings of IEEE Cluster Computing<\/i>, Indianapolis, IN, September 2013.<\/p>\n

Optimizations on a Parallel File System Integrated with Object-Based Storage Devices<\/strong><\/a>
\nCengiz Karakoyunlu<\/a> and John A. Chandy<\/a>
\nin Proceedings of IEEE Cluster Computing<\/i>, Indianapolis, IN, September 2013.<\/p>\n

Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs<\/strong><\/a>
\nSupriya Karmakar<\/a>, John A. Chandy<\/a>, and Faquir C. Jain<\/a>
\nin IEEE Transactions on Very Large Scale Integration (VLSI) Systems
\n<\/i>, vol. 21, no. 5, pp. 793-806, May 2013<\/p>\n

A Case for Optimistic Coordination in HPC Storage Systems<\/strong><\/a>
\nPhilip Carns, Kevin Harms, Dries Kimpe, Robert Ross, Justin Wozniak, Lee Ward, Matthew Curry, Ruth Klundt, Geoff Danielson, Cengiz Karakoyunlu<\/a>, John Chandy<\/a>, Bradley Settlemeyer, and William Gropp
\nin Proceedings of Petascale Data Storage Workshop<\/i>, Salt Lake City, UT, November 2012.<\/p>\n

Quaternary Logic and Applications using Multiple Quantum Well Based SWSFETs<\/strong><\/a>
\nPawan Gogna, Murali Lingalugari, John A. Chandy<\/a>, Evan Heller, E.-S. Hasaneen, and Faquir Jain<\/a>
\nin International Journal of VLSI Design and Communication Systems<\/i>, vol. 3, no. 5, pp. 27-42, October 2012.<\/p>\n

Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II-VI Barrier Layers<\/strong><\/a>
\nFaquir Jain<\/a>, Supriya Karmakar<\/a>, Pik-Yiu Chan, Ernesto Suarez, Mukesh Gogna, John A. Chandy<\/a>, and Evan Heller
\nin Journal of Electronic Materials<\/i>, vol. 41, no. 10 pp. 2775-2784, October 2012.<\/p>\n

Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors<\/strong><\/a>
\nSupriya Karmakar<\/a>, John A. Chandy<\/a>, Mukesh Gogna, and Faquir C. Jain<\/a>
\nin Journal of Electronic Materials<\/i>, vol. 41, no. 8 pp. 2184-2192, Aug. 2012<\/p>\n

Techniques for an Energy Aware Parallel File System<\/strong><\/a>
\nCengiz Karakoyunlu<\/a> and John A. Chandy<\/a>
\nin Proceedings of International Green Computing Conference: Energy Consumption and Reliability of Storage Systems<\/i>, San Jose, CA, pp. 13-17, June 2012.<\/p>\n

An Active Storage Framework for Object Storage Devices<\/strong><\/a>
\nMichael T. Runde<\/a>, Wesley G. Stevens, Paul A. Wortman<\/a>, and John A. Chandy<\/a>
\nin Proceedings of IEEE Conference on Massive Data Storage<\/i>, Pacific Grove, CA, April 2012.<\/p>\n

A Non-blocking Switching Network and Routing Algorithm for On-Chip Networks<\/strong><\/a>
\nAjithkumar Thamarakuzhi<\/a> and John A. Chandy<\/a>
\nin Procedia Engineering<\/i>, vol. 30, pp. 997-1004, 2012.<\/p>\n

2-Dilated Flattened Butterfly: A Nonblocking Switching Topology for High-Radix Networks<\/strong><\/a>
\nAjithkumar Thamarakuzhi<\/a> and John A. Chandy<\/a>
\nin Computer Communications<\/i>, vol. 34, no. 15, pp. 1822-1835, September 15, 2011.<\/p>\n

Spatial Wavefunction-Switched (SWS)-FET: A Novel Device to Process Multiple Bits Simultaneously with Sub-Picosecond Delays<\/strong><\/a>
\nS. Karmakar<\/a>, J. A. Chandy<\/a>, and F.C. Jain<\/a>
\nin International Journal of High Speed Electronics and Systems<\/i>, vol. 20, no. 3, pp. 653-668, September 2011.<\/p>\n

Application of 25 nm Quantum Dot Gate FETs to the Design of ADC and DAC Circuits<\/strong><\/a>
\nF.C. Jain<\/a>, J. A. Chandy<\/a>, B. Miller, E.-S. Hasaneen, and E. Heller
\nin International Journal of High Speed Electronics and Systems<\/i>, vol. 20, no. 3, pp. 641-652, September 2011.<\/p>\n

Spatial Wavefunction Switched (SWS) InGaAs FETs with II-VI Gate Insulators<\/strong><\/a>
\nF.C. Jain<\/a>, B. Miller, E. Suarez, P-Y. Chan, S. Karmakar<\/a>, F. Al-Amoody, M. Gogna, J. Chandy<\/a>, and E. Heller
\nin Journal of Electronic Materials<\/i>, vol. 40, no. 8, pp. 1717-1726, Aug. 2011<\/p>\n

Design and Implementation of a Nonblocking 2-Dilated Flattened Butterfly Switching Network<\/strong><\/a>
\nAjithkumar Thamarakuzhi<\/a> and John A. Chandy<\/a>
\nin IEEE Latin America Transactions<\/i>, vol. 9, no. 4, pp. 557-564, July 2011<\/p>\n

Active Storage Networks for Accelerating K-Means Data Clustering<\/strong><\/a>
\nJanardhan Singaraju<\/a> and John A. Chandy<\/a>
\nin Proceedings of the Symposium on Applied Reconfigurable Computing<\/i>, March 2011<\/p>\n

Adaptive Load Balanced Routing for 2-Dilated Flattened Butterfly Switching Network<\/strong><\/a>
\nAjithkumar Thamarakuzhi<\/a> and John A. Chandy<\/a>
\nin Proceedings of the International Conference on Networks<\/i>, January 2011, Best Paper Award<\/p>\n

Parallel data sort using networked FPGAs<\/b>
\n<\/a>Janardhan Singaraju<\/a> and John A. Chandy<\/a>
\nin Proceedings of the International Conference on ReConFigurable Computing and FPGAs<\/i>, December 2010<\/p>\n

Design and Implementation of a Nonblocking 2-Dilated Flattened Butterfly Switching Network<\/strong><\/a>
\nAjithkumar Thamarakuzhi<\/a> and John A. Chandy<\/a>
\nin Proceedings of the IEEE Latin American Conference on Communications<\/i>, September 2010<\/p>\n

Scaling the NetFPGA switch using Aurora over SATA <\/strong><\/a>
\nAjithkumar Thamarakuzhi<\/a> and John A. Chandy<\/a>
\nin Proceedings of the NetFPGA Developers Workshop<\/i>, August 2010<\/p>\n

User space storage system stack modules with file level control<\/strong><\/a>
\nSumit Narayan<\/a>, Rohit K. Mehta, and John A. Chandy<\/a>
\nin Proceedings of the Annual Linux Symposium<\/i>, July 2010<\/p>\n

I\/O Characterization on a Parallel File System<\/strong><\/a>
\nSumit Narayan<\/a> and John A. Chandy<\/a>
\nin Proceedings of the International Symposium on Performance Evaluation of Computer and Telecommunication Systems<\/i>, July 2010<\/p>\n

2-Dilated Flattened Butterfly: A Nonblocking Switching Network <\/strong><\/a>
\nAjithkumar Thamarakuzhi<\/a> and John A. Chandy<\/a>
\nin Proceedings of the International Conference on High Performance Switching and Routing<\/i>, June 2010<\/p>\n

Extendable storage framework for reliable clustered storage systems<\/strong><\/a>
\nSumit Narayan<\/a> and John A. Chandy<\/a>
\nin Proceedings of IEEE IPDPS PhD Forum<\/i>. June 2010.<\/p>\n

3-state Quantum Dot Gate FETs in Desigining High Sampling Rate ADCs <\/b>
\nS. Karmakar<\/a>, John A. Chandy<\/a>, and F.C. Jain<\/a>
\nin Proceedings of the NST Nanotechnology Conference and Expo<\/i>, June 2010<\/p>\n

Uncovering Errors: The Cost of Detecting Silent Data Corruption <\/strong><\/a>
\nSumit Narayan<\/a>, John A. Chandy<\/a>, Sam Lang, Philip Carns, and Rob Ross
\nin Proceedings of the 4th Petascale Data Storage Workshop (PDSW)<\/i> held in conjunction with IEEE\/ACM Supercomputing 2009, Portland, OR. November 2009.<\/p>\n

ATTEST: ATTribute-based Extendable STorage<\/strong><\/a>
\nSumit Narayan<\/a> and John A. Chandy<\/a>
\nin Journal of Systems and Software<\/i>, vol. 83, no. 4, pp. 548-556, November 2009.<\/p>\n

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators<\/strong><\/a>
\nF.C. Jain<\/a>, E. Suarez, M. Gogna, F. Alamoody, D. Butkiewicus, R. Hohner, T. Liaskas, S. Karmakar<\/a>, P.-Y. Chan, B. Miller, J. Chandy<\/a>, and E. Heller
\nin Journal of Electronic Materials<\/i>, vol. 38, no. 8, pp. 1574-1578, August 2009<\/p>\n

An Analysis of Parallel Programming Techniques for Data Intensive Computation<\/strong><\/a>
\nAnuradharthi Thiruvenkata Ramani<\/a> and John A. Chandy<\/a>
\nin Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA)<\/i>, Las Vegas, NV, July 2009<\/p>\n

An Analysis of Resource Costs in a Public Computing Grid<\/strong><\/a>
\nJohn A. Chandy<\/a>
\nin Proceedings of International Parallel and Distributed Processing Symposium Workshop on Desktop Grids and Volunteer Computing Systems<\/i>. May 2009.<\/p>\n

FEARLESS: Flash Enabled Active Replication of Low End Survivable Storage<\/strong><\/a>
\nVamsi Kundeti and John A. Chandy<\/a>
\nin Proceedings of the International Workshop on Integrating Solid-state Memory into the Storage Hierarchy (WISH)<\/i>, Washington, DC, March 2009.<\/p>\n

Hardware parallelism vs. software parallelism<\/strong><\/a>
\nJohn A. Chandy<\/a> and Janardhan Singaraju<\/a>
\nin Proceedings of the USENIX Workshop on Hot Topics in Parallelism (HotPar)<\/i>, Berkeley, CA, March 2009<\/p>\n

Modeling and Fabrication of Cladded Ge Quantum Dot Gate Silicon MOSFETs Exhibiting 3-State Behavior<\/strong><\/a>
\nF. Jain<\/a>, M. Gogna, F. Alamoody, S. Karmakar<\/a>, E. Suarez, J. Chandy<\/a>, and E. Heller
\nin Proceedings of MRS Fall Meeting Symposium A: Performance and Reliability of Semiconductor Device<\/i>, December 2008<\/p>\n

RAID0.5: Design and Implementation of a Low Cost Disk Array Data Protection Architecture<\/strong><\/a>
\nJohn A. Chandy<\/a>
\nin Journal of Supercomputing<\/i>, vol. 46, no. 2, pp. 108-123, November 2008.<\/p>\n

Active Storage using Object-Based Devices<\/strong><\/a>
\nTina Miriam John<\/a>, Anuradharthi Thiruvenkata Ramani<\/a>, and John A. Chandy<\/a>
\nin Proceedings of International Workshop on High Performance I\/O Systems and Data Intensive Computing (HiperIO)<\/i>, Tsukuba, Japan, October 2008.<\/p>\n

FPGA Based String Matching for Network Processing Applications<\/strong><\/a>
\nJanardhan Singaraju<\/a> and John A. Chandy<\/a>
\nin Microprocessors and Microsystems<\/i>, Vol. 32, No. 4, pages 210-222, June 2008.<\/p>\n

A Generalized Replica Placement Strategy to Optimize Latency in a Wide Area Distributed Storage System<\/strong><\/a>
\nJohn A. Chandy<\/a>
\nin Proceedings of International Workshop on Data Aware Distributed Computing<\/i>, Boston, MA, June 2008.<\/p>\n

Multiple Valued Logic Using 3-State Quantum Dot Gate FETs<\/strong><\/a>
\nJohn A. Chandy<\/a> and Faquir C. Jain<\/a>
\nin Proceedings of International Symposium on Multiple Valued Logic <\/i>, Dallas, TX, pp. 186-190, May 2008<\/p>\n

Quantum Dot Gate Field-Effect Transistors Configured as 3-state FETs and Nonvolatile Memory Devices for Mixed Signal Circuits<\/b>
\nF. Jain<\/a>, R. Velampati, A. Rodriguez, E. Heller, E.-S. Hasaneen, J. Chandy<\/a>, B. I. Miller and F. Papadimitrakopoulos.
\nin Proceedings of Connecticut Microelectronics and Optoelectronics Symposium,<\/i> pages 9–12. April 2008.<\/p>\n

Device and circuit modeling using novel 3-state quantum dot gate FETs<\/strong><\/a>
\nFaquir C. Jain<\/a>, E. Heller, Supriya Karmarkar and John Chandy<\/a>
\nin Proceedings of International Semiconductor Device Research Symposium<\/i>. Dec. 2007.<\/p>\n

Dual Actuator Logging Disk Architecture and Modeling<\/strong><\/a>
\nJohn A. Chandy<\/a>
\nin Journal of Systems Architecture<\/i>, Vol. 53, No. 12, pages 913-926, December 2007.<\/p>\n

Parity Redundancy in a Clustered Storage System<\/strong><\/a>
\nSumit Narayan<\/a> and John A. Chandy<\/a>
\nin Proceedings of International Workshop on Storage and Network Architecture and Parallel I\/Os<\/i>, San Diego, CA, Sept. 2007<\/p>\n

Reliability Tradeoffs in Personal Storage Systems<\/strong><\/a>
\nJohn A. Chandy<\/a> and Sumit Narayan<\/a>
\nin ACM Operating Systems Review<\/i>, Vol. 41, No. 1, pages 37-41, January 2007.<\/p>\n

A Case for Active Storage Networks in High Performance Computing<\/b>
\nJohn A. Chandy<\/a>
\nin Proceedings of Boston Area Architecture Workshop,<\/i> pages 23–24. Jan. 2007.<\/p>\n

A CAM-based Keyword Match Processor Architecture<\/strong><\/a>
\nLong Bu and John A. Chandy<\/a>
\nin Microelectronics Journal<\/i>, Vol. 38, No. 8, pages 828-836, August 2006.<\/p>\n

A Generic Lookup Cache Architecture for Network Processing Applications<\/strong><\/a>
\nJanardhan Singaraju<\/a> and John A. Chandy<\/a>
\nin Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms<\/a><\/i>, Las Vegas, NV, pp. 247-248, June 2006.<\/p>\n

RAID0.5: Active Data Replication for Low Cost Disk Array Data Protection<\/strong><\/a>
\nJohn A. Chandy<\/a>
\nin Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications<\/a><\/i>, Las Vegas, NV, pp. 963-969, June 2006.<\/p>\n

Storage Allocation in Unreliable Peer-to-Peer Systems<\/strong><\/a>
\nJohn A. Chandy<\/a>
\nin Proceedings of International Conference on Dependable Systems and Networks<\/a><\/i>, Philadelphia, PA, June 2006, pp. 227-236.<\/p>\n

A Quorum Based Content Delivery Architecture<\/strong><\/a>
\nMichael P. Kapralos<\/a> and John A. Chandy<\/a>
\nin Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications<\/a><\/i>, Las Vegas, NV, June 2005.<\/p>\n

A Signature Match Processor Architecture for Network Intrusion Detection<\/strong><\/a>
\nJanardhan Singaraju<\/a>, Long Bu and John A. Chandy<\/a>
\nin Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, April 2005<\/p>\n

Trace Based Analysis of File System Effects on Disk I\/O<\/strong><\/a>
\nSumit Narayan<\/a> and John A. Chandy<\/a>
\nin Proceedings of International Symposium on Performance Evaluation of Computer and Telecommunication Systems, San Jose, CA, July 2004<\/p>\n

A Keyword Match Processor Architecture Using Content Addressable Memory<\/strong><\/a>
\nLong Bu and John A. Chandy<\/a>
\nin Proceedings of Great Lakes Symposium on VLSI, Boston, MA, April 2004<\/p>\n

FPGA Based Network Intrusion Detection using Content Addressable Memories<\/strong><\/a>
\nLong Bu and John A. Chandy<\/a>
\nin Proceedings of IEEE Symposium on Field-Programmable Custom Computing
\nMachines, Napa, CA, April 2004<\/p>\n

Parity Redundancy Strategies in a Large Scale Distributed Storage System<\/strong><\/a>
\nJohn A. Chandy<\/a>
\nin Proceedings of IEEE Conference on Mass Storage Systems and Technologies<\/a><\/i>, Adelphi, MD, April 2004, pp. 185-192<\/p>\n

Data Integrity in a Distributed Storage System<\/strong><\/a>
\nJonathan D. Bright and John A. Chandy<\/a>
\nin Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications<\/a><\/i>, Las Vegas, NV, June 2003.<\/p>\n

A Dual Actuator Logging Disk Architecture<\/strong><\/a>
\nJohn A. Chandy<\/a>
\nin Proceedings of IASTED International Conference on Computer Science and Technology, Cancun, Mexico, May 2003.<\/p>\n

A Scalable Architecture for Clustered Network Attached Storage<\/strong><\/a>
\nJonathan D. Bright and John A. Chandy<\/a>
\nin Proceedings of IEEE Symposium on Mass Storage Systems and Technologies, San Diego, CA, April 2003, pp. 196-206<\/p>\n

A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement<\/strong><\/a>
\nJohn A. Chandy<\/a> and Prithviraj Banerjee.<\/a>
\nin Journal of Parallel and Distributed Computing<\/i>, Vol. 57, No. 1, pages 65-90, April 1999.<\/p>\n

WADE: A Web-based Automated Parallel CAD Environment<\/strong><\/a>
\nD. R. Chakrabarti, Pramod G. Joisha<\/a>, John A. Chandy<\/a>, Dilip Krishnaswamy<\/a>, Venkat Krishnaswamy<\/a>, and Prithviraj Banerjee<\/a>
\nin Proceedings of HiPC’98 5th International Conference on High Performance Computing, Chennai, India, December 1998.<\/p>\n

A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement<\/b>
\nJohn A. Chandy<\/a> and Prithviraj Banerjee<\/a>
\nTechnical Report CPDC-TR-9801-001, Center for Parallel and Distributed Computing, Northwestern University, Evanston, IL, January 1998<\/p>\n

A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement<\/strong><\/a>
\nJohn A. Chandy<\/a> and Prithviraj Banerjee<\/a>
\nin Proceedings of International Conference on Computer Design, Austin, TX, October 1997<\/p>\n

Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors<\/strong><\/a>
\nJ. G. Holm<\/a>, John A. Chandy<\/a>, Steven Parkes<\/a>, Sumit Roy<\/a>, Venkat Krishnaswamy<\/a>, Gagan Hasteer<\/a>, and Prithviraj Banerjee<\/a>
\nin Proceedings of ACM International Conference on Supercomputing, Vienna, Austria, July 1997<\/p>\n

An Evaluation of Parallel Simulated Annealing Strategies with Application to Standard Cell Placement<\/strong><\/a>
\nJohn A. Chandy<\/a>, Sungho Kim<\/a>, Balkrishna Ramkumar<\/a>, Steven Parkes<\/a>, and Prithviraj Banerjee.<\/a>
\nin IEEE Transactions on Computer-Aided Design<\/i>, April 1997.<\/p>\n

Parallel Global Routing Algorithms for Standard Cells<\/strong><\/a>
\nZhaoyun Xing<\/a>, John A. Chandy<\/a>, and Prithviraj Banerjee<\/a>
\nin Proceedings of International Parallel Processing Symposium, Geneva, Switzerland, April 1997<\/p>\n

Distributed Object Oriented Data Structures and Algorithms for VLSI CAD<\/strong><\/a>
\nJohn A. Chandy<\/a>, Steven Parkes<\/a>, and Prithviraj Banerjee<\/a>
\nin Proceedings of International Workshop on Parallel Algorithms for Irregularly Structured Problems, Santa Barbara, CA, August 1996<\/p>\n

Parallel Algorithms for Standard Cell Placement Using Simulated Annealing<\/strong><\/a>
\nJohn A. Chandy<\/a>
\nPhD dissertation, Department of Electrical Engineering, University of Illinois, Urbana, IL, Technical Report CRHC-96-10\/UILU-ENG-96-2216, July 1996<\/p>\n

Parallel Simulated Annealing Strategies for VLSI Cell Placement<\/strong><\/a>
\nJohn A. Chandy<\/a> and Prithviraj Banerjee<\/a>
\nin Proceedings of the International Conference on VLSI Design<\/a>, Bangalore, India, January 1996<\/p>\n

The PARADIGM Compiler for Distributed-Memory Multicomputers<\/strong><\/a>
\nPrithviraj Banerjee<\/a>, John A. Chandy<\/a>, Manish Gupta<\/a>, Eugene W. Hodges IV<\/a>, John G. Holm<\/a>, Antonio Lain<\/a>, Daniel J. Palermo<\/a>, Shankar Ramaswamy<\/a>, and Ernesto Su<\/a>.
\nin IEEE Computer<\/i>, Vol. 28, No. 10, pages 37-47, October 1995.<\/p>\n

Parallel Algorithms for Logic Synthesis Using the MIS Approach<\/strong><\/a>
\nKaushik De<\/a>, John A. Chandy<\/a>, Sumit Roy<\/a>, Steven Parkes<\/a>, and Prithviraj Banerjee<\/a>
\nin Proceedings of the International Parallel Processing Symposium<\/a><\/i>, Santa Barbara, CA, April 1995<\/p>\n

The PARADIGM Compiler for Distributed-Memory Message Passing Multicomputers<\/strong><\/a>
\nP. Banerjee<\/a>, J. A. Chandy<\/a>, M. Gupta<\/a>, J. G. Holm<\/a>, A. Lain<\/a>, D. J. Palermo<\/a>, S. Ramaswamy<\/a>, and E. Su<\/a>
\nin the First International Workshop on Parallel Processing, pages 322-330, Bangalore, India, December 1994.<\/p>\n

A Library-based Approach to Portable, Parallel, Object-Oriented Programming: Interface, Implementation, and Application<\/strong><\/a>
\nSteven Parkes<\/a>, John A. Chandy<\/a>, and Prithviraj Banerjee<\/a>
\nin Proceedings of Supercomputing ’94<\/a><\/i>, Washington, DC, November 1994, pp. 69-78.<\/p>\n

Communication Optimizations for Distributed Memory Multicomputers used in the PARADIGM Compiler<\/strong><\/a>
\nD. J. Palermo<\/a>, E. Su<\/a>, J. A. Chandy<\/a>, and P. Banerjee.<\/a>
\nin Proceedings of the 23rd International Conference on Parallel Processing, pages II:1-10, St. Charles, IL, August 1994.<\/p>\n

ProperPLACE: A Portable Parallel Algorithm for Cell Placement<\/strong><\/a>
\nSungho Kim<\/a>, John A. Chandy<\/a>, Steven Parkes<\/a>, Balkrishna Ramkumar<\/a>, and Prithviraj Banerjee<\/a>
\nin Proceedings of the International Parallel Processing Symposium<\/a><\/i>, Cancun, Mexico, April 1994.<\/p>\n

ProperCAD II: A Run-Time Library for Portable, Parallel, Object-Oriented Programming with Applications to VLSI CAD<\/strong><\/a>
\nSteven Parkes<\/a>, John A. Chandy<\/a>, and Prithviraj Banerjee<\/a>
\nTechnical Report CRHC-93-22\/UILU-ENG-93-2250, Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL, December 1993<\/p>\n

Reliability Evaluation of Disk Array Architectures<\/strong><\/a>
\nJohn A. Chandy<\/a> and Prithviraj Banerjee.<\/a>
\nin Proceedings of the 22nd International Conference on Parallel Processing, St. Charles, IL, August 1993.<\/p>\n

Failure Evaluation of Disk Array Organizations<\/strong><\/a>
\nJohn Chandy<\/a> and A. L. N. Reddy<\/a>
\nin Proceedings of the 1993 International Conference on Distributed Computing Systems, Pittsburgh, PA, May 1993.<\/p>\n

Design and Evaluation of Gracefully Degradable Disk Arrays<\/strong><\/a>
\nA. L. N. Reddy<\/a>, John Chandy<\/a>, and Prithviraj Banerjee.<\/a>
\nin Journal of Parallel and Distributed Computing<\/i>, Vol. 17, No. 1, pp. 28-40, January 1993.<\/p>\n

An Evaluation of Disk Array Reliability and Performance<\/b><\/a>
\nJohn A. Chandy<\/a>
\nM.S. thesis, Department of Electrical Engineering, University of
\nIllinois, Urbana, IL, Technical Report CRHC-92-28, December 1992<\/p>\n","protected":false},"excerpt":{"rendered":"

List publications By Topic Publication List Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic F. Jain, R. H. Gudlavalleti, R. Mays, B. Saman, J. Chandy, and Evan Heller Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications, pp. 187-197, November 2021. 3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched […]<\/p>\n","protected":false},"author":60,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-2","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.ee.uconn.edu\/john-chandy\/wp-json\/wp\/v2\/pages\/2","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.ee.uconn.edu\/john-chandy\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.ee.uconn.edu\/john-chandy\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.ee.uconn.edu\/john-chandy\/wp-json\/wp\/v2\/users\/60"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ee.uconn.edu\/john-chandy\/wp-json\/wp\/v2\/comments?post=2"}],"version-history":[{"count":18,"href":"https:\/\/www.ee.uconn.edu\/john-chandy\/wp-json\/wp\/v2\/pages\/2\/revisions"}],"predecessor-version":[{"id":140,"href":"https:\/\/www.ee.uconn.edu\/john-chandy\/wp-json\/wp\/v2\/pages\/2\/revisions\/140"}],"wp:attachment":[{"href":"https:\/\/www.ee.uconn.edu\/john-chandy\/wp-json\/wp\/v2\/media?parent=2"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}