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Publication List by Topic
- Security
- Storage Systems
- Reconfigurable Computing
- Parallel Algorithms and Systems
- VLSI CAD
- Semiconductor Devices
- On-Chip Networks
- Misc
Security
Zero Trust for Hardware Supply Chains: Challenges in Application of Zero Trust Principles to Hardware
D. DiMase, Z. A. Collier, J. Muldavin, J. A. Chandy, D. Davidson, D. Doran, U. Guin, J. Hallman, J. Heebink, E. Hall, A. R. Shaffer
National Defense Industrial Association White Paper, October 2021.
Bit2RNG: Leveraging Bad-page Initialized Table with Bit-error Insertion for True Random Number Generation in Commodity Flash Memory
W. Yan H. Zhu, Z. Yu, F. Tehranipoor, J. Chandy, N. Zhang, and X. Zhang
Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust, December 2020.
Exploring the Coverage of Existing Hardware Vulnerabilities in Community Standards
Paul A. Wortman, Fatemeh Tehranipoor and John A. Chandy.
in Proceedings of Silicon Valley Cybersecurity Conference. pp. 87-97. December 2020.
FLASH: FPGA Locality Associated Secure Hash for Nearest Neighbor Search and Clustering Application
W. Yan, F. Tehranipoor, X. Zhang, and J. Chandy
Proceedings of International Conference on Field-Programmable Logic and Applications, pp. 249-253, September 2020.
A Holistic Approach to Cyber Physical Systems Security and Resilience
D. DiMase, Z.A. Collier, John Chandy, B.S. Cohen, G. D’Anna, H. Dunlap, J. Hallman, J. Mandelbaum, J. Ritchie, and L. Vessels
IEEE Systems Security Symposium, pp. 1-8, July 2020,
SMART: security model adversarial risk-based tool for systems security design evaluation
P. A. Wortman and John A. Chandy
in Journal of Cybersecurity. vol. 6, no. 1. Feb. 2020.
Embedded Systems Authentication and Encryption using Strong PUF Modeling
S. Enamul Quadir and John.A. Chandy
International Conference on Consumer Electronics, Jan. 2020.
Key Generation for Hardware Obfuscation using Strong PUFs
S. Enamul Quadir and John.A. Chandy
Cryptography, vol. 3, no. 2. July 2019.
Engineering for Vehicle Cybersecurity
D. DiMase, Z.A. Collier, J. A. Chandy, P. Bronn, K. Heffner and S. Walters.
in Cybersecurity for Commercial Vehicles SAE. 2019.
P2M-based security model: security enhancement using combined PUF and PRNG models for authenticating consumer electronic devices
Paul Wortman, Wei Yan, John A. Chandy, and Fatemeh Tehranipoor in IET Computers and Digital Techniques, vol. 12, no. 66, pp. 289-296, November 2018.
Low Pass Filter PUF: Authentication of Printed Circuit Boards Based on Resistor and Capacitor Variations
S. Enamul Quadir and John A. Chandy.
International Journal of High Speed Electronics and Systems, vol 27. Sept./Dec. 2018.
Phase Calibrated Ring Oscillator PUF Design and Application
Wei Yan and John Chandy
Computers, vol 7. July 2018.
DVFT: A Lightweight Solution for Power Supply Noise-based TRNG using Dynamic Voltage Feedback Tuning System
F. Tehranipoor, P. Wortman, N. Karimian, W. Yan, and J. A. Chandy
in IEEE Transactions on VLSI Systems, vol. 26, no. 6, pp. 1084-1097, June 2018
An Adversarial Risk-based Approach for Network Architecture Security Modeling and Design
P. A. Wortman and John A. Chandy
in Proceedings of Cyber Security 2018. Jun 2018.
Error Tolerant ASCA on FPGA
C. Ma, and J,A. Chandy
International Conference on Cloud Computing and Security, pp. 563-572, June 2018
Framework for Design Exploration of Secure Embedded System Development
Paul A. Wortman, Fatemeh Tehranipoor and John A. Chandy.
in Proceedings of Conference on Systems Engineering Research. May 2018.
An Overview of DRAM-Based Security Primitives
N.A. Anagnostopoulos, S. Katzenbeisser, J. Chandy, and F. Tehranipoor
in Cryptography , vol. 2(2), no. 7, March 2018
Low-cost Authentication Paradigm for Consumer Electronics Within the Internet of Wearable Fitness Tracking Applications
Fatemeh Tehranipoor, Nima Karimian, Paul A. Wortman, and John A. Chandy
in Proceedings of IEEE International Conference on Consumer Electronics, January 2018.
Exploring Methods of Authentication for the Internet of Things
F. Tehranipoor, N. Karimian, P.A. Wortman, A. Haque, J. Fahrny, and J. A. Chandy
in Internet of Things: Challenges, Advances, and Applications, ed. By Q.F. Hassan, A.u.R. Khan, and S.A. Madani, 2018.
Influence of Error and Hamming Weights on ASCA
C. Ma, J. Chandy, L. Michel, F. Liu and W. Cruz.
in Proceedings of International Conference on Information Security and Cryptology. November 2017.
Phase calibrated ring oscillator PUF design and implementation on FPGAs
Wei Yan, Chenglu Jin, Fatemeh Tehranipoor, and John A. Chandy
in Proceedings of International Conference on Field-Programmable Logic and Applications, Ghent, Belgium, Sept. 2017.
PUF-based Fuzzy Authentication without Error Correcting Codes
Wei Yan, Fatemeh Tehranipoor, and John A. Chandy
in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 9, pp. 1445-1457, Sept. 2017.
DRNG: DRAM-based random number generation using its startup value behavior
Charles Eckert, Fatemeh Tehranipoor, and John A. Chandy
in Proceedings of IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, August 2017.
Insights into the Potential Usage of the Initial Values of DRAM Arrays of Commercial Off-the-Shelf Devices for Security Applications
N. A. Anagnostopoulos, Andre Schaller, Yufan Fan, Wenjie Xiong, Fatemeh Tehranipoor, Tolga Arul, Sebastian Gabmeyer, Jakub Szefer, John A. Chandy and Stefan Katzenbeisser.
in 2017 Crypto-Day Proceedings. Jun 2017.
Algebraic Side-Channel Attack on Twofish
Chujiao Ma, John A. Chandy, and Zhijie Shi
in Journal of Internet Services and Information Security, vol. 7, no. 2, pp. 32-43, May 2017.
Investigation of DRAM PUFs reliability under device accelerated aging effects
Fatemeh Tehranipoor, Nima Karimian, Wei Yan, and John A. Chandy
in Proceedings of IEEE International Symposium on Circuits and Systems, May 2017.
CHASE Survey of Technology Needs
S. Enamul Quadir, Daniel DiMase and John A. Chandy
in GOMACTech. March 2017.
DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication
Fatemeh Tehranipoor, Nima Karimian, Wei Yan, and John A. Chandy
in IEEE Transactions on VLSI Systems, vol. 25, no. 3, pp. 1085-1097, March 2017.
Proposing a modeling framework for minimizing security vulnerabilities in IoT systems in the healthcare domain
Paul A. Wortman, Fatemeh Tehranipoor, Nima Karimian and John A. Chandy
in Proceedings of IEEE EMBS International Conference on Biomedical and Health Informatics, February 2017.
A Study of Power Supply Variation as a Source of Random Noise
Fatemeh Tehranipoor, Nima Karimian, Wei Yan, and John A. Chandy
in Proceedings of IEEE International Conference on VLSI Design, January 2017.
A Survey on Chip to System Reverse Engineering
S.E. Quadir, J. Chen, D. Forte, N. Asadizanjani, S. Shahbazmohamadi, L. Wang, John Chandy, and M. Tehranipoor in ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 1, article 6, May 2016
Robust hardware true random number generators using DRAM remanence effects
Fatemeh Tehranipoor, Wei Yan, and John A. Chandy
in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust, McLean, VA, pp. 79-84, May 2016.
A Novel Way to Authenticate Untrusted Integrated Circuits
Wei Yan, Fatemeh Tehranipoor, and John A. Chandy
in Proceedings of International Conference on Computer-Aided Design, Austin, TX, pp. 132-138, November 2015.
Hardware Hacking: An Approach to Trustable Computing Systems Security Education
John A. Chandy, Zhijie Shi, Mohammad Tehranipoor, Megan Welsh, Chujiao Ma, Qihang Shi, and Ujjwal Guin
in Colloquium for Information Systems Security Education, Las Vegas, NV, June 2015.
DRAM based Intrinsic Physical Unclonable Functions for System Level Security
Fatemeh Tehranipoor, Nima Karimian, Kan Xiao, and John A. Chandy
in Proceedings of ACM Great Lakes Symposium on VLSI,Pittsburgh, PA,pp. 15-20, May 2015.
Storage Systems
A Trace-Based Study of SMB Network File System Workloads in an Academic Enterprise
Paul A. Wortman and John.A. Chandy
Proceedings of International Symposium on Performance Evaluation of Computer and Telecommunication Systems, July 2020.
Adding Data Analytics Capabilities to Scaled-out Object Store
Cengiz Karakoyunlu, John A. Chandy, and Alma Riska in Journal of Systems and Software, vol. 121, pp. 16-27, November 2016.
Exploiting User Metadata for Energy-Aware Node Allocation in a Cloud Storage System
Cengiz Karakoyunlu and John A. Chandy
in Journal of Computer and System Sciences, vol. 82, no. 2, pp. 282-309, March 2016.
Leveraging Checkpoint/Restore to Optimize Utilization of Cloud Compute Resources
Rohit Mehta and John A. Chandy
in Proceedings of IEEE Workshop on Cloud-Based Networks and ApplicationsClearwater Beach, FL, pp. 714-721, October 2015.
Using an Object-Based Active Storage Framework to Improve Parallel Storage
Cengiz Karakoyunlu, Michael Runde, and John A. Chandy
in Proceedings of Workshop on Interfaces and Architectures for Scientific Data Storage Minneapolis, MN, Sept. 2014.
Creating a programmable object storage stack
Orko Momin, Cengiz Karakoyunlu, Michael T. Runde, and John A. Chandy
in Proceedings of the Programmable File Systems Workshop , Vancouver, CANADA, June 2014.
An object interface storage node for clustered file systems
Orko Momin and John A. Chandy
in Proceedings of IEEE Cluster Computing, Indianapolis, IN, September 2013.
Optimizations on a Parallel File System Integrated with Object-Based Storage Devices
Cengiz Karakoyunlu and John A. Chandy
in Proceedings of IEEE Cluster Computing, Indianapolis, IN, September 2013.
A Case for Optimistic Coordination in HPC Storage Systems
Philip Carns, Kevin Harms, Dries Kimpe, Robert Ross, Justin Wozniak, Lee Ward, Matthew Curry, Ruth Klundt, Geoff Danielson, Cengiz Karakoyunlu, John Chandy, Bradley Settlemeyer, and William Gropp
in Proceedings of Petascale Data Storage Workshop, Salt Lake City, UT, November 2012.
Techniques for an Energy Aware Parallel File System
Cengiz Karakoyunlu and John A. Chandy
in Proceedings of International Green Computing Conference: Energy Consumption and Reliability of Storage Systems, San Jose, CA, pp. 13-17, June 2012.
An Active Storage Framework for Object Storage Devices
Michael T. Runde, Wesley G. Stevens, Paul A. Wortman, and John A. Chandy
in Proceedings of IEEE Conference on Massive Data Storage, Pacific Grove, CA, April 2012.
User space storage system stack modules with file level control
Sumit Narayan, Rohit K. Mehta, and John A. Chandy
in Proceedings of the Annual Linux Symposium, July 2010
I/O Characterization on a Parallel File System
Sumit Narayan and John A. Chandy
in Proceedings of the International Symposium on Performance Evaluation of Computer and Telecommunication Systems, July 2010
Extendable storage framework for reliable clustered storage systems
Sumit Narayan and John A. Chandy
in Proceedings of IEEE IPDPS PhD Forum. June 2010.
Uncovering Errors: The Cost of Detecting Silent Data Corruption
Sumit Narayan, John A. Chandy, Sam Lang, Philip Carns, and Rob Ross
in Proceedings of the 4th Petascale Data Storage Workshop (PDSW) held in conjunction with IEEE/ACM Supercomputing 2009, Portland, OR. November 2009.
ATTEST: ATTribute-based Extendable STorage
Sumit Narayan and John A. Chandy
in Journal of Systems and Software, vol. 83, no. 4, pp. 548-556, November 2009.
FEARLESS: Flash Enabled Active Replication of Low End Survivable Storage
Vamsi Kundeti and John A. Chandy
in Proceedings of the International Workshop on Integrating Solid-state Memory into the Storage Hierarchy (WISH), Washington, DC, March 2009.
RAID0.5: Design and Implementation of a Low Cost Disk Array Data Protection Architecture
John A. Chandy
in Journal of Supercomputing, vol. 46, no. 2, pp. 108-123, November 2008.
Active Storage using Object-Based Devices
Tina Miriam John, Anuradharthi Thiruvenkata Ramani, and John A. Chandy
in Proceedings of International Workshop on High Performance I/O Systems and Data Intensive Computing (HiperIO), Tsukuba, Japan, October 2008.
A Generalized Replica Placement Strategy to Optimize Latency in a Wide Area Distributed Storage System
John A. Chandy
in Proceedings of International Workshop on Data Aware Distributed Computing, Boston, MA, June 2008.
Dual Actuator Logging Disk Architecture and Modeling
John A. Chandy
in Journal of Systems Architecture, Vol. 53, No. 12, pages 913-926, December 2007.
Parity Redundancy in a Clustered Storage System
Sumit Narayan and John A. Chandy
in Proceedings of International Workshop on Storage and Network Architecture and Parallel I/Os, San Diego, CA, Sept. 2007
Reliability Tradeoffs in Personal Storage Systems
John A. Chandy and Sumit Narayan
in ACM Operating Systems Review, Vol. 41, No. 1, pages 37-41, January 2007.
RAID0.5: Active Data Replication for Low Cost Disk Array Data Protection
John A. Chandy
in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, pp. 963-969, June 2006.
Storage Allocation in Unreliable Peer-to-Peer Systems
John A. Chandy
in Proceedings of International Conference on Dependable Systems and Networks, Philadelphia, PA, June 2006, pp. 227-236.
A Quorum Based Content Delivery Architecture
Michael P. Kapralos and John A. Chandy
in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, June 2005.
Trace Based Analysis of File System Effects on Disk I/O
Sumit Narayan and John A. Chandy
in Proceedings of International Symposium on Performance Evaluation of Computer and Telecommunication Systems, San Jose, CA, July 2004
Parity Redundancy Strategies in a Large Scale Distributed Storage System
John A. Chandy
in Proceedings of IEEE Conference on Mass Storage Systems and Technologies, Adelphi, MD, April 2004, pp. 185-192
Data Integrity in a Distributed Storage System
Jonathan D. Bright and John A. Chandy
in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, June 2003.
A Dual Actuator Logging Disk Architecture
John A. Chandy
in Proceedings of IASTED International Conference on Computer Science and Technology, Cancun, Mexico, May 2003.
A Scalable Architecture for Clustered Network Attached Storage
Jonathan D. Bright and John A. Chandy
in Proceedings of IEEE Symposium on Mass Storage Systems and Technologies, San Diego, CA, April 2003, pp. 196-206
Reliability Evaluation of Disk Array Architectures
John A. Chandy and Prithviraj Banerjee.
in Proceedings of the 22nd International Conference on Parallel Processing, St. Charles, IL, August 1993.
Failure Evaluation of Disk Array Organizations
John Chandy and A. L. N. Reddy
in Proceedings of the 1993 International Conference on Distributed Computing Systems, Pittsburgh, PA, May 1993.
Design and Evaluation of Gracefully Degradable Disk Arrays
A. L. N. Reddy, John Chandy, and Prithviraj Banerjee.
in Journal of Parallel and Distributed Computing, Vol. 17, No. 1, pp. 28-40, January 1993.
An Evaluation of Disk Array Reliability and Performance
John A. Chandy
M.S. thesis, Department of Electrical Engineering, University of Illinois, Urbana, IL, Technical Report CRHC-92-28, December 1992
Reconfigurable Computing
HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion
Michael Kapralos and John A. Chandy
in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 2019.
Active Storage Networks: Using Embedded Computation in the Network Switch for Cluster Data Processing
Janardhan Singaraju, Ajithkumar Thamarakuzhi and John A. Chandy
in Future Generation Computer Systems, vol. 45, pp. 149-160, April 2015.
Active Storage Networks for Accelerating K-Means Data Clustering
Janardhan Singaraju and John A. Chandy
in Proceedings of the Symposium on Applied Reconfigurable Computing, March 2011
Parallel data sort using networked FPGAs
Janardhan Singaraju and John A. Chandy
in Proceedings of the International Conference on ReConFigurable Computing and FPGAs, December 2010
Scaling the NetFPGA switch using Aurora over SATA
Ajithkumar Thamarakuzhi and John A. Chandy
in Proceedings of the NetFPGA Developers Workshop, August 2010
Hardware parallelism vs. software parallelism
John A. Chandy and Janardhan Singaraju
in Proceedings of the USENIX Workshop on Hot Topics in Parallelism (HotPar), Berkeley, CA, March 2009
FPGA Based String Matching for Network Processing Applications
Janardhan Singaraju and John A. Chandy
in Microprocessors and Microsystems, Vol. 32, No. 4, pages 210-222, June 2008.
A Case for Active Storage Networks in High Performance Computing
John A. Chandy
in Proceedings of Boston Area Architecture Workshop, pages 23–24. Jan. 2007.
A CAM-based Keyword Match Processor Architecture
Long Bu and John A. Chandy
in Microelectronics Journal, Vol. 38, No. 8, pages 828-836, August 2006.
A Generic Lookup Cache Architecture for Network Processing Applications
Janardhan Singaraju and John A. Chandy
in Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, NV, pp. 247-248, June 2006.
A Signature Match Processor Architecture for Network Intrusion Detection
Janardhan Singaraju, Long Bu and John A. Chandy
in Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, April 2005
A Keyword Match Processor Architecture Using Content Addressable Memory
Long Bu and John A. Chandy
in Proceedings of Great Lakes Symposium on VLSI, Boston, MA, April 2004
FPGA Based Network Intrusion Detection using Content Addressable Memories
Long Bu and John A. Chandy
in Proceedings of IEEE Symposium on Field-Programmable Custom Computing
Machines, Napa, CA, April 2004
Parallel Algorithms and Systems
An Analysis of Parallel Programming Techniques for Data Intensive Computation
Anuradharthi Thiruvenkata Ramani and John A. Chandy
in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), Las Vegas, NV, July 2009
An Analysis of Resource Costs in a Public Computing Grid
John A. Chandy
in Proceedings of International Parallel and Distributed Processing Symposium Workshop on Desktop Grids and Volunteer Computing Systems. May 2009.
Distributed Object Oriented Data Structures and Algorithms for VLSI CAD
John A. Chandy, Steven Parkes, and Prithviraj Banerjee
in Proceedings of International Workshop on Parallel Algorithms for Irregularly Structured Problems, Santa Barbara, CA, August 1996
The PARADIGM Compiler for Distributed-Memory Multicomputers
Prithviraj Banerjee, John A. Chandy, Manish Gupta, Eugene W. Hodges IV, John G. Holm, Antonio Lain, Daniel J. Palermo, Shankar Ramaswamy, and Ernesto Su.
in IEEE Computer, Vol. 28, No. 10, pages 37-47, October 1995.
The PARADIGM Compiler for Distributed-Memory Message Passing Multicomputers
P. Banerjee, J. A. Chandy, M. Gupta, J. G. Holm, A. Lain, D. J. Palermo, S. Ramaswamy, and E. Su
in the First International Workshop on Parallel Processing, pages 322-330, Bangalore, India, December 1994.
A Library-based Approach to Portable, Parallel, Object-Oriented Programming: Interface, Implementation, and Application
Steven Parkes, John A. Chandy, and Prithviraj Banerjee
in Proceedings of Supercomputing ’94, Washington, DC, November 1994, pp. 69-78.
Communication Optimizations for Distributed Memory Multicomputers used in the PARADIGM Compiler
D. J. Palermo, E. Su, J. A. Chandy, and P. Banerjee.
in Proceedings of the 23rd International Conference on Parallel Processing, pages II:1-10, St. Charles, IL, August 1994.
ProperCAD II: A Run-Time Library for Portable, Parallel, Object-Oriented Programming with Applications to VLSI CAD
Steven Parkes, John A. Chandy, and Prithviraj Banerjee
Technical Report CRHC-93-22/UILU-ENG-93-2250, Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL, December 1993
VLSI CAD
A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement
John A. Chandy and Prithviraj Banerjee.
in Journal of Parallel and Distributed Computing, Vol. 57, No. 1, pages 65-90, April 1999.
WADE: A Web-based Automated Parallel CAD Environment
D. R. Chakrabarti, Pramod G. Joisha, John A. Chandy, Dilip Krishnaswamy, Venkat Krishnaswamy, and Prithviraj Banerjee
in Proceedings of HiPC’98 5th International Conference on High Performance Computing, Chennai, India, December 1998.
PS (147K)
A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement
John A. Chandy and Prithviraj Banerjee
Technical Report CPDC-TR-9801-001, Center for Parallel and Distributed Computing, Northwestern University, Evanston, IL, January 1998
A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement
John A. Chandy and Prithviraj Banerjee
in Proceedings of International Conference on Computer Design, Austin, TX, October 1997
Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors
J. G. Holm, John A. Chandy, Steven Parkes, Sumit Roy, Venkat Krishnaswamy, Gagan Hasteer, and Prithviraj Banerjee
in Proceedings of ACM International Conference on Supercomputing, Vienna, Austria, July 1997
An Evaluation of Parallel Simulated Annealing Strategies with Application to Standard Cell Placement
John A. Chandy, Sungho Kim, Balkrishna Ramkumar, Steven Parkes, and Prithviraj Banerjee.
in IEEE Transactions on Computer-Aided Design, April 1997.
Parallel Global Routing Algorithms for Standard Cells
Zhaoyun Xing, John A. Chandy, and Prithviraj Banerjee
in Proceedings of International Parallel Processing Symposium, Geneva, Switzerland, April 1997
Parallel Algorithms for Standard Cell Placement Using Simulated Annealing
John A. Chandy
PhD dissertation, Department of Electrical Engineering, University of Illinois, Urbana, IL, Technical Report CRHC-96-10/UILU-ENG-96-2216, July 1996
Parallel Simulated Annealing Strategies for VLSI Cell Placement
John A. Chandy and Prithviraj Banerjee
in Proceedings of the International Conference on VLSI Design, Bangalore, India, January 1996
Parallel Algorithms for Logic Synthesis Using the MIS Approach
Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, and Prithviraj Banerjee
in Proceedings of the International Parallel Processing Symposium, Santa Barbara, CA, April 1995
ProperPLACE: A Portable Parallel Algorithm for Cell Placement
Sungho Kim, John A. Chandy, Steven Parkes, Balkrishna Ramkumar, and Prithviraj Banerjee
in Proceedings of the International Parallel Processing Symposium, Cancun, Mexico, April 1994.
Semiconductor Devices
Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic
F. Jain, R. H. Gudlavalleti, R. Mays, B. Saman, J. Chandy, and Evan Heller
Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications, pp. 187-197, November 2021.
3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs
B. Saman, R. H. Gudlavalleti, R. R. Mays, J. Chandy, Evan Heller and F. Jain
Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications, pp. 139-150, November 2021.
Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs
H. Salama, B. Saman, R. Gudlavalleti, R. Mays, E. Heller, J. Chandy, and F. Jain
Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications, pp. 129-138, November 2021.
3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL)
F. Jain, B. Saman, R. H. Gudlavalleti, R. Mays, J. Chandy, and Evan Heller
Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications, pp. 103-118, November 2021.
A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array
R. H. Gudlavalleti, B. Saman, R. Mays, H. Salama, Evan Heller, J. Chandy, and F. Jain,
Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications, pp. 83-92, November 2021.
Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic
F. Jain, B. Saman, R. Gudlavalleti, R. Mays, J. Chandy and E. Heller
Journal of Electronic Materials, March 2021.
Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations
R. H. Gudlavalleti, B. Saman, R. Mays, M. Lingalugari, E. Heller, J. Chandy, and F. Jain
Nanotechnology for Electronics, Photonics, Biosensors, and Emerging Technologies, pp. 135-142, September 2020.
Simulation of Stacked Quantum Dot Channels SWS-FET Using Multi-FET ABM Modeling
H. Salama, B. Saman, R. H. Gudlavalleti, P-Y. Chan, R. Mays, B. Khan, E. Heller, J. Chandy, and F. Jain
Nanotechnology for Electronics, Photonics, Biosensors, and Emerging Technologies, pp. 129-133, September 2020.
Eight-bit ADC using non-volatile flash memory
S. Karmakar, J. A. Chandy, and F.C. Jain.
IET Circuits, Devices & Systems, 13(1):98-102. Jan. 2019.
Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Ge Quantum Dot Channel for Faster Erasing
M. Lingalugari, E. Heller, B. Parthasarathy, J. Chandy, and F. Jain
in International Journal of High Speed Electronics and Systems, vol. 27, issue 01, March/June 2018.
Circuits and Simulation of Quaternary SRAM Using Quantum Dot Channel Field Effect Transistors (QDC-FETs)
B. Saman, J. Kundo, J. Chandy, and F.C. Jain
in International Journal of High Speed Electronics and Systems, vol. 27, issue 01, March/June 2018
QD floating gate NVRAM using QD channel for faster erasing
M. Lingalugari, P-Y. Chan, E.K. Heller, J. Chandy, and F.C. Jain
in Electronics Letters, vol. 54, no. 1, pp. 36-37. January 2018
Multi-bit NVRAMs Using Quantum Dot Gate Access Channel
M. Lingalugari, P-Y. Chan, J. Chandy, E.K. Heller, and F.C. Jainn
in International Journal of High Speed Electronics and Systems, vol. 26, no. 3, September 2017
Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation
B. Saman, P. Gogna, E.-S. Hasaneen, J. Chandy, E.K. Heller, and F.C. Jain
in International Journal of High Speed Electronics and Systems, vol. 26, no. 3, September 2017
Quantum Dot Channel (QDC) FETs with Wraparound II-VI Gate Insulators: Numerical Simulations
Faquir Jain, Murali Lingalugari, Jun Kundo, Pial Mirdha, Ernesto Suarez, John A. Chandy, and Evan Heller in Journal of Electronic Materials, vol. 45, no. 11, pp. 5663-5670, November 2016.
Novel Multiplexer Design Using Multi-State Spatial Wavefunction-Switched (SWS) FETs
Pial Mirdha, Murali Lingalugari, Evan K. Heller, John
A. Chandy, and Faquir C. Jain
in International Journal of High Speed Electronics and Systems, vol. 24, issue 03, no. 04, Sept./Dec. 2015.
Si and InGaAs Spatial Wavefunction-Switched (SWS) FETs with II–VI Gate Insulators: An Approach to the Design and Integration of Two-Bit SRAMs and Binary CMOS Logic
Faquir Jain, Pik-Yiu Chan, Murali Lingalugari, Jun Kondo, Ernesto Suarez, Pawan Gogna, John Chandy, and Evan Heller in Journal of Electronic Materials, vol. 44, no. 9, pp. 3109-3115, September 2015.
Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs
Supriya Karmakar, John A. Chandy, and Faquir C. Jain in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 4, pp. 609-618, April 2015.
Ge-ZnSSe Spatial Wavefunction Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic
Pawan Gogna, Ernesto Suarez, Murali Lingalugari, John Chandy, Evan Heller, E.-S. Hasaneen, and Faquir C. Jain
in Journal of Electronic Materials , vol. 42, no. 11, pp. 3337-3343, November 2013.
Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers
Faquir Jain, Pik-Yiu Chan, Ernesto Suarez, Murali Lingalugari, Jun Kondo, Pawan Gogna, Barry Miller, John Chandy, and Evan Heller
in Journal of Electronic Materials, vol. 42, no. 11, pp. 3191-3202, November 2013.
Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators
Murali Lingalugari, Kavitha Baskar, Pik-Yiu Chan, P. Dufilie, Ernesto Suarez, John Chandy, Evan Heller, E.-S. Hasaneen, and Faquir C. Jain
in Journal of Electronic Materials, vol. 42, no. 11, pp. 3156-3163, November 2013
Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs
Supriya Karmakar, John A. Chandy, and Faquir C. Jain
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol. 21, no. 5, pp. 793-806, May 2013
Quaternary Logic and Applications using Multiple Quantum Well Based SWSFETs
Pawan Gogna, Murali Lingalugari, John A. Chandy, Evan Heller, E.-S. Hasaneen, and Faquir Jain
in International Journal of VLSI Design and Communication Systems, vol. 3, no. 5, pp. 27-42, October 2012.
Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II-VI Barrier Layers
Faquir Jain, Supriya Karmakar, Pik-Yiu Chan, Ernesto Suarez, Mukesh Gogna, John A. Chandy, and Evan Heller
in Journal of Electronic Materials, vol. 41, no. 10 pp. 2775-2784, October 2012.
Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors
Supriya Karmakar, John A. Chandy, Mukesh Gogna, and Faquir C. Jain
in Journal of Electronic Materials, vol. 41, no. 8 pp. 2184-2192, Aug. 2012
Spatial Wavefunction-Switched (SWS)-FET: A Novel Device to Process Multiple Bits Simultaneously with Sub-Picosecond Delays
S. Karmakar, J. A. Chandy, and F.C. Jain
in International Journal of High Speed Electronics and Systems, vol. 20, no. 3, pp. 653-668, September 2011.
Application of 25 nm Quantum Dot Gate FETs to the Design of ADC and DAC Circuits
F.C. Jain, J. A. Chandy, B. Miller, E.-S. Hasaneen, and E. Heller
in International Journal of High Speed Electronics and Systems, vol. 20, no. 3, pp. 641-652, September 2011.
Spatial Wavefunction Switched (SWS) InGaAs FETs with II-VI Gate Insulators
F.C. Jain, B. Miller, E. Suarez, P-Y. Chan, S. Karmakar, F. Al-Amoody, M. Gogna, J. Chandy, and E. Heller
in Journal of Electronic Materials, vol. 40, no. 8, pp. 1717-1726, Aug. 2011
3-state Quantum Dot Gate FETs in Desigining High Sampling Rate ADCs
S. Karmakar, John A. Chandy, and F.C. Jain
in Proceedings of the NST Nanotechnology Conference and Expo, June 2010
Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators
F.C. Jain, E. Suarez, M. Gogna, F. Alamoody, D. Butkiewicus, R. Hohner, T. Liaskas, S. Karmakar, P.-Y. Chan, B. Miller, J. Chandy, and E. Heller
in Journal of Electronic Materials, vol. 38, no. 8, pp. 1574-1578, August 2009
Modeling and Fabrication of Cladded Ge Quantum Dot Gate Silicon MOSFETs Exhibiting 3-State Behavior
F. Jain, M. Gogna, F. Alamoody, S. Karmakar, E. Suarez, J. Chandy, and E. Heller
in Proceedings of MRS Fall Meeting Symposium A: Performance and Reliability of Semiconductor Device, December 2008
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs
John A. Chandy and Faquir C. Jain
in Proceedings of International Symposium on Multiple Valued Logic , Dallas, TX, pp. 186-190, May 2008
Quantum Dot Gate Field-Effect Transistors Configured as 3-state FETs and Nonvolatile Memory Devices for Mixed Signal Circuits
F. Jain, R. Velampati, A. Rodriguez, E. Heller, E.-S. Hasaneen, J. Chandy, B. I. Miller and F. Papadimitrakopoulos.
in Proceedings of Connecticut Microelectronics and Optoelectronics Symposium, pages 9–12. April 2008.
Device and circuit modeling using novel 3-state quantum dot gate FETs
Faquir C. Jain, E. Heller, Supriya Karmarkar and John Chandy
in Proceedings of International Semiconductor Device Research Symposium. Dec. 2007.
On-Chip Networks
A Non-blocking Switching Network and Routing Algorithm for On-Chip Networks
Ajithkumar Thamarakuzhi and John A. Chandy
in Procedia Engineering, vol. 30, pp. 997-1004, 2012.
2-Dilated Flattened Butterfly: A Nonblocking Switching Topology for High-Radix Networks
Ajithkumar Thamarakuzhi and John A. Chandy
in Computer Communications, vol. 34, no. 15, pp. 1822-1835, September 15, 2011.
Design and Implementation of a Nonblocking 2-Dilated Flattened Butterfly Switching Network
Ajithkumar Thamarakuzhi and John A. Chandy
in IEEE Latin America Transactions, vol. 9, no. 4, pp. 557-564, July 2011
Adaptive Load Balanced Routing for 2-Dilated Flattened Butterfly Switching Network
Ajithkumar Thamarakuzhi and John A. Chandy
in Proceedings of the International Conference on Networks, January 2011, Best Paper Award
Design and Implementation of a Nonblocking 2-Dilated Flattened Butterfly Switching Network
Ajithkumar Thamarakuzhi and John A. Chandy
in Proceedings of the IEEE Latin American Conference on Communications, September 2010
2-Dilated Flattened Butterfly: A Nonblocking Switching Network
Ajithkumar Thamarakuzhi and John A. Chandy
in Proceedings of the International Conference on High Performance Switching and Routing, June 2010
Misc
A design flow with integrated verification of requirements and faults in safety-critical systems
Wei Yan, Daniel Fontaine, John A. Chandy, and Laurent Michel
in Proceedings of System of Systems Engineering Conference, Hawaii, June 2017.